`timescale 1ns/1ns
`define Txports 4
`define Rxports 4

module top;
	parameter int NumTx = `Txports;
	parameter int NumRx = `Rxports;

	logic rst, clk;
	initial begin
		rst = 1'b0;
		clk = 1'b0;

		#5 rst = 1'b1;
		#5 clk = 1'b1;

		#5 rst = 1'b0;
		   clk = 1'b0;
	end
	forever
		#5 clk = ~clk;
	end

Utopia Tx[0:NumTx-1] ();
Utopia Rx[0:NumRx-1] ();

cpu_ifc mif();
squat # (NumRx, NumTx) squat (Rx, Tx, mif, rst, clk);
test # (NumRx, NumTx) t1 (Rx, Tx, mif, rst, clk);

endmodule:top

program automatic test

endprogram

interface cpu_ifc ();

endinterface:cpu_ifc

typedef virtual cpu_ifc.Test vCPU_T;